init
This commit is contained in:
commit
7946b8004a
65
VGA_Driver.vhd
Executable file
65
VGA_Driver.vhd
Executable file
@ -0,0 +1,65 @@
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Library IEEE;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity VGA_Driver is
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port(
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clk :in std_logic;
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areset_l :in std_logic;
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data_en :out std_logic;
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HSYNC :out std_logic;
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VSYNC :out std_logic
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);
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end VGA_Driver;
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architecture wrapper of VGA_Driver is
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component VGA_Vert is
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port(
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clk :in std_logic;
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areset_l :in std_logic;
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trig :in std_logic;
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data_en :out std_logic;
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sync_v :out std_logic
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);
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end component;
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component vga_hrz is
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port(
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clk : in std_logic;
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rst_l : in std_logic;
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data_en : out std_logic;
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sync_en : out std_logic;
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trigger : out std_logic
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);
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end component;
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signal h_done :std_logic;
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signal v_data_en :std_logic;
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signal h_data_en :std_logic;
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begin
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data_en<=v_data_en and h_data_en;
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Vertical : VGA_Vert
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port map(
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clk =>clk,
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areset_l =>areset_l,
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trig =>h_done,
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data_en =>v_data_en,
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sync_v =>VSYNC
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);
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Horizontal : vga_hrz
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port map(
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clk =>clk,
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rst_l =>areset_l,
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data_en =>h_data_en,
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sync_en =>HSYNC,
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trigger =>h_done
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);
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end wrapper;
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89
VGA_Vert.vhd
Executable file
89
VGA_Vert.vhd
Executable file
@ -0,0 +1,89 @@
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Library IEEE;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity VGA_Vert is
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port(
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clk :in std_logic;
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areset_l :in std_logic;
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trig :in std_logic;
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data_en :out std_logic;
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sync_v :out std_logic
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);
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end VGA_Vert;
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architecture behave of VGA_Vert is
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type state is (sync, data);
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signal PS,NS :state;
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signal count :integer;
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begin
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syncProc : process(clk,areset_l)
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begin
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if(areset_l='0')then
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PS<=sync;
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elsif(rising_edge(clk))then
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PS<=NS;
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end if;
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end process syncProc;
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countProc : process(clk,areset_l,trig)
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begin
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if(areset_l='0')then
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count<=0;
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elsif(rising_edge(clk))then
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if(PS=data and NS=sync)then
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count<=0;
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else
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if(trig='1')then
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count<=count+1;
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end if;
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end if;
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end if;
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end process countProc;
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stateProc : process (PS,count)
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begin
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case PS is
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when sync=>
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if(count>=44)then
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NS<=data;
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else
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NS<=sync;
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end if;
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when data=>
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if(count>=524)then
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NS<=sync;
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else
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NS<=data;
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end if;
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end case;
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end process stateProc;
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outputProc : process(PS, count)
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begin
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case PS is
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when sync =>
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data_en<='0';
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if(count>9 and count<12)then
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sync_v<='0';
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else
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sync_v<='1';
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end if;
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when data=>
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data_en<='1';
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sync_v<='1';
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end case;
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end process outputProc;
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end behave;
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60
counter.vhd
Executable file
60
counter.vhd
Executable file
@ -0,0 +1,60 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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generic (
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size : integer :=4;
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div : integer :=1
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);
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port(
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clk : in std_logic;
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areset_l : in std_logic;
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enable : in std_logic;
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max_count : in std_logic_vector(size-1 downto 0);
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count_out : out std_logic_vector(size-1 downto 0);
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done : out std_logic
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);
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end counter;
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architecture behave of counter is
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signal max_unsigned : unsigned (size-1 downto 0);
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signal count : unsigned (size-1 downto 0);
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begin
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runProc : process(clk, areset_l)
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variable delay : integer :=0;
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begin
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if(areset_l ='0')then
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count <=(others=>'0');
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delay :=0;
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done<='0';
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elsif(rising_edge(clk))then
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if(enable='1')then
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if(delay=(div-1))then
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delay:=0;
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if(count<max_unsigned)then
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count <=count +1;
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done<='0';
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elsif(count>=max_unsigned)then
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count<=(others=>'0');
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done<='1';
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end if;
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else
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delay:= delay+1;
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done<='0';
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end if;
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else
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delay:=delay;
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count<=count;
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done<='0';
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end if;
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end if;
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end process runProc;
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count_out <=std_logic_vector(count);
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max_unsigned<=unsigned(max_count);
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end behave;
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89
full6seg7.vhd
Executable file
89
full6seg7.vhd
Executable file
@ -0,0 +1,89 @@
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity full6seg7 is
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port(
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clk :in std_logic;
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areset_l :in std_logic;
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value_in :in std_logic_vector(23 downto 0);
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dec_value :in std_logic_vector(5 downto 0) :="000000";
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hex_out0 :out std_logic_vector(7 downto 0);
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hex_out1 :out std_logic_vector(7 downto 0);
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hex_out2 :out std_logic_vector(7 downto 0);
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hex_out3 :out std_logic_vector(7 downto 0);
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hex_out4 :out std_logic_vector(7 downto 0);
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hex_out5 :out std_logic_vector(7 downto 0)
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);
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end full6seg7;
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architecture wrapper of full6seg7 is
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component seg7Driver is
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port(
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clk: in std_logic;
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rst_l: in std_logic;
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dec: in std_logic;
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cnt: in std_logic_vector(3 downto 0); --current count from counter modules
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seg7: out std_logic_vector(7 downto 0)
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);
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end component;
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begin
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seg0 : seg7Driver
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port map(
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clk =>clk,
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rst_l =>areset_l,
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dec =>dec_value(0),
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cnt =>value_in(3 downto 0),
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seg7 =>hex_out0
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);
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seg1 : seg7Driver
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port map(
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clk =>clk,
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rst_l =>areset_l,
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dec =>dec_value(1),
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cnt =>value_in(7 downto 4),
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seg7 =>hex_out1
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);
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seg2 : seg7Driver
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port map(
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clk =>clk,
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rst_l =>areset_l,
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dec =>dec_value(2),
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cnt =>value_in(11 downto 8),
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seg7 =>hex_out2
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);
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seg3 : seg7Driver
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port map(
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clk =>clk,
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rst_l =>areset_l,
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dec =>dec_value(3),
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cnt =>value_in(15 downto 12),
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seg7 =>hex_out3
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);
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seg4 : seg7Driver
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port map(
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clk =>clk,
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rst_l =>areset_l,
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dec =>dec_value(4),
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cnt =>value_in(19 downto 16),
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seg7 =>hex_out4
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);
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seg5 : seg7Driver
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port map(
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clk =>clk,
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rst_l =>areset_l,
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dec =>dec_value(5),
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cnt =>value_in(23 downto 20),
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seg7 =>hex_out5
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);
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end wrapper;
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49
lfsr.vhd
Executable file
49
lfsr.vhd
Executable file
@ -0,0 +1,49 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity lfsr is
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port(
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clk: in std_logic;
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rst_l: in std_logic;
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gen: in std_logic;
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num: out std_logic_vector(7 downto 0)
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);
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end entity lfsr;
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architecture behavioral of lfsr is
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signal b: std_logic := '0';
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signal shift: std_logic_vector(15 downto 0):= X"81A5";
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signal genrising :std_logic;
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signal r0 :std_logic;
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signal r1 :std_logic;
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--stored from left to right, so 16 is located in LSB
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begin
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num <= shift(3) & shift(10) & shift(11) & shift(4) & shift(14) & shift(1) & shift(9) & shift(6); --picking 8 bits
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b <= shift(0) xor shift(1) xor shift(3) xor shift(12);
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process(clk, gen, rst_l)
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begin
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if (rst_l = '0') then
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shift <= X"81A5";
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elsif(rising_edge(clk)) then
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if(genrising='1') then
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-- x^16 + x^15 + x^13 + x^4
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shift <= b & shift(15 downto 1);
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end if;
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end if;
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end process;
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genProc : process(clk, rst_l)
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begin
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if(rst_l='0')then
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r0<='0';
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r1<='0';
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elsif(rising_edge(clk))then
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r0<=gen;
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r1<=r0;
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end if;
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end process genProc;
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genrising<=not r1 and r0;
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end architecture behavioral;
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58
seg7Driver.vhd
Executable file
58
seg7Driver.vhd
Executable file
@ -0,0 +1,58 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity seg7Driver is
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port(
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clk: in std_logic;
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rst_l: in std_logic;
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dec: in std_logic;
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cnt: in std_logic_vector(3 downto 0); --current count from counter modules
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seg7: out std_logic_vector(7 downto 0)
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);
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end entity seg7Driver;
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--six 7-seg displays:
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-- '.' : 0x80
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-- '0' : 0x3f
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-- '1' : 0x06
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-- '2' : 0x5b
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-- '3' : 0x4f
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-- '4' : 0x66
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-- '5' : 0x6d
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-- '6' : 0x7d
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-- '7' : 0x07
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-- '8' : 0x7f
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-- '9' : 0x6f
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architecture behavioral of seg7Driver is
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type table is array(0 to 15) of std_logic_vector(6 downto 0);
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constant segLUT: table := (
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"0111111", --0
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"0000110", --1
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"1011011", --2
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"1001111", --3
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"1100110", --4
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"1101101", --5
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"1111101", --6
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"0000111", --7
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"1111111", --8
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"1101111", --9
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"1110111", --A
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"1111100", --b
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"0111001", --C
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"1011110", --d
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"1111001", --E
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"1110001"); --F
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signal table_entry: std_logic_vector(6 downto 0);
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begin
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seg7 <= not (dec & table_entry);
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process(clk, rst_l)
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begin
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if (rst_l = '0') then --active low reset
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table_entry <= segLUT(0);
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elsif (rising_edge(clk)) then
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table_entry <= segLUT(to_integer(unsigned(cnt)));
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end if;
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end process;
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end architecture behavioral;
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87
vga_hrz.vhd
Executable file
87
vga_hrz.vhd
Executable file
@ -0,0 +1,87 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vga_hrz is
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port(
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clk : in std_logic;
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rst_l : in std_logic;
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data_en : out std_logic;
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sync_en : out std_logic;
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trigger : out std_logic
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);
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end entity;
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architecture behavioral of vga_hrz is
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type state_type is (FTP, HSYNC, BKP, PIX);
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signal current_state, next_state : state_type := FTP;
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signal clk_cnt : integer := 0;
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signal cnt_rst : std_logic;
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begin
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process(rst_l, clk)
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begin
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if (rst_l = '0') then
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current_state <= FTP;
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clk_cnt <= 0;
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elsif (rising_edge(clk)) then
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current_state <= next_state;
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if (cnt_rst = '1') then --signals state change from other process
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clk_cnt <= 0;
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else
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clk_cnt <= clk_cnt + 1;
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end if;
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end if;
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end process;
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process(current_state, clk_cnt)
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begin
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case current_state is
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when FTP =>
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trigger <= '0';
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data_en <= '0';
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sync_en <= '1';
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if (clk_cnt < 15) then --16 clks
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next_state <= FTP;
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cnt_rst <= '0';
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else
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next_state <= HSYNC;
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cnt_rst <= '1';
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end if;
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when HSYNC =>
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trigger <= '0';
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data_en <= '0';
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sync_en <= '0';
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if (clk_cnt < 95) then --96 clks
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next_state <= HSYNC;
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cnt_rst <= '0';
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else
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next_state <= BKP;
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cnt_rst <= '1';
|
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end if;
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when BKP =>
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trigger <= '0';
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data_en <= '0';
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sync_en <= '1';
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if (clk_cnt < 47) then --48clks
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next_state <= BKP;
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cnt_rst <= '0';
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else
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next_state <= PIX;
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cnt_rst <= '1';
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end if;
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when PIX =>
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data_en <= '1';
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sync_en <= '1';
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if (clk_cnt < 639) then --640 pixels
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next_state <= PIX;
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trigger <= '0';
|
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cnt_rst <= '0';
|
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else
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next_state <= FTP;
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trigger <= '1';
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cnt_rst <= '1';
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end if;
|
||||
end case;
|
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end process;
|
||||
end architecture behavioral;
|
||||
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