59 lines
1.4 KiB
VHDL
Executable File
59 lines
1.4 KiB
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity seg7Driver is
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port(
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clk: in std_logic;
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rst_l: in std_logic;
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dec: in std_logic;
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cnt: in std_logic_vector(3 downto 0); --current count from counter modules
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seg7: out std_logic_vector(7 downto 0)
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);
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end entity seg7Driver;
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--six 7-seg displays:
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-- '.' : 0x80
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-- '0' : 0x3f
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-- '1' : 0x06
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-- '2' : 0x5b
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-- '3' : 0x4f
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-- '4' : 0x66
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-- '5' : 0x6d
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-- '6' : 0x7d
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-- '7' : 0x07
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-- '8' : 0x7f
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-- '9' : 0x6f
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architecture behavioral of seg7Driver is
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type table is array(0 to 15) of std_logic_vector(6 downto 0);
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constant segLUT: table := (
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"0111111", --0
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"0000110", --1
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"1011011", --2
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"1001111", --3
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"1100110", --4
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"1101101", --5
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"1111101", --6
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"0000111", --7
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"1111111", --8
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"1101111", --9
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"1110111", --A
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"1111100", --b
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"0111001", --C
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"1011110", --d
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"1111001", --E
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"1110001"); --F
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signal table_entry: std_logic_vector(6 downto 0);
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begin
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seg7 <= not (dec & table_entry);
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process(clk, rst_l)
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begin
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if (rst_l = '0') then --active low reset
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table_entry <= segLUT(0);
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elsif (rising_edge(clk)) then
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table_entry <= segLUT(to_integer(unsigned(cnt)));
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end if;
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end process;
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end architecture behavioral;
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