commit 7946b8004afef37a7adfdd4e70a74e8c03afeece
Author: youngcw <calebyoung94@gmail.com>
Date:   Mon Feb 12 09:45:51 2024 -0700

    init

diff --git a/VGA_Driver.vhd b/VGA_Driver.vhd
new file mode 100755
index 0000000..ef46ade
--- /dev/null
+++ b/VGA_Driver.vhd
@@ -0,0 +1,65 @@
+Library IEEE;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+entity VGA_Driver is
+    port(
+        clk         :in std_logic;
+        areset_l    :in std_logic;
+
+        data_en     :out std_logic;
+        HSYNC       :out std_logic;
+        VSYNC       :out std_logic
+    );
+end VGA_Driver;
+
+architecture wrapper of VGA_Driver is
+
+    component  VGA_Vert is
+    port(
+        clk         :in std_logic;
+        areset_l    :in std_logic;
+        trig        :in std_logic;
+        data_en     :out std_logic;
+        sync_v      :out std_logic
+    );
+    end component;
+
+    component  vga_hrz is
+    port(
+        clk     : in std_logic;
+        rst_l   : in std_logic;
+        data_en : out std_logic;
+        sync_en : out std_logic;
+        trigger : out std_logic
+        );
+    end component;
+
+    signal h_done       :std_logic;
+    signal v_data_en    :std_logic;
+    signal h_data_en    :std_logic;
+
+begin
+
+    data_en<=v_data_en and h_data_en;
+
+    Vertical : VGA_Vert
+    port map(
+        clk         =>clk,
+        areset_l    =>areset_l,
+        trig        =>h_done,
+        data_en     =>v_data_en,
+        sync_v      =>VSYNC
+    );
+
+    Horizontal : vga_hrz
+    port map(
+        clk         =>clk,
+        rst_l       =>areset_l,
+        data_en     =>h_data_en,
+        sync_en     =>HSYNC,
+        trigger     =>h_done
+    );
+
+
+end wrapper;
\ No newline at end of file
diff --git a/VGA_Vert.vhd b/VGA_Vert.vhd
new file mode 100755
index 0000000..578b856
--- /dev/null
+++ b/VGA_Vert.vhd
@@ -0,0 +1,89 @@
+Library IEEE;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+entity VGA_Vert is
+    port(
+        clk         :in std_logic;
+        areset_l    :in std_logic;
+        trig        :in std_logic;
+
+        data_en     :out std_logic;
+        sync_v      :out std_logic
+    );
+end VGA_Vert;
+
+architecture behave of VGA_Vert is
+
+    type state is (sync, data);
+    signal PS,NS        :state;
+    signal count        :integer;
+
+
+begin
+
+    syncProc : process(clk,areset_l)
+    begin
+        if(areset_l='0')then
+            PS<=sync;
+        elsif(rising_edge(clk))then
+            PS<=NS;
+        end if;
+    end process syncProc;
+
+    countProc : process(clk,areset_l,trig)
+    begin
+        if(areset_l='0')then
+            count<=0;
+        elsif(rising_edge(clk))then
+            if(PS=data and NS=sync)then
+                count<=0;
+            else
+                if(trig='1')then
+                    count<=count+1;
+                end if;
+            end if;
+        end if;
+    end process countProc;
+
+    stateProc : process (PS,count)
+    begin
+        case PS is
+            when sync=>
+                if(count>=44)then
+                    NS<=data;
+                else
+                    NS<=sync;
+                end if;
+            
+            when data=>
+                if(count>=524)then
+                    NS<=sync;
+                else
+                    NS<=data;
+                end if;
+
+        end case;
+    end process stateProc;
+
+    outputProc : process(PS, count)
+    begin
+        case PS is
+            when sync =>
+                data_en<='0';
+                if(count>9 and count<12)then
+                    sync_v<='0';
+                else
+                    sync_v<='1';
+                end if;
+            
+            when data=>
+                data_en<='1';
+                sync_v<='1';
+            
+        end case;
+    end process outputProc;
+                
+
+
+end behave;
diff --git a/counter.vhd b/counter.vhd
new file mode 100755
index 0000000..ec0642f
--- /dev/null
+++ b/counter.vhd
@@ -0,0 +1,60 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity counter is
+	generic (
+        size : integer :=4;
+        div  : integer :=1
+    );
+    port(
+        clk         : in    std_logic;
+        areset_l    : in    std_logic;
+        enable      : in    std_logic;
+        max_count   : in    std_logic_vector(size-1 downto 0);
+        count_out   : out   std_logic_vector(size-1 downto 0);
+        done        : out   std_logic
+    );
+end counter;
+
+architecture behave of counter is
+    signal max_unsigned : unsigned (size-1 downto 0);
+    signal count : unsigned (size-1 downto 0);
+    
+begin
+    runProc : process(clk, areset_l)
+        variable delay : integer :=0;
+    begin
+        if(areset_l ='0')then
+            count <=(others=>'0');
+            delay :=0;
+            done<='0';
+        elsif(rising_edge(clk))then
+            if(enable='1')then
+                if(delay=(div-1))then
+                    delay:=0;
+                    if(count<max_unsigned)then
+                        count <=count +1;
+                        done<='0';
+                    elsif(count>=max_unsigned)then
+                        count<=(others=>'0');
+                        done<='1';
+                    end if;
+                else
+                    delay:= delay+1;
+                    done<='0';
+                end if;
+            else
+                delay:=delay;
+                count<=count;
+                done<='0';
+            end if;
+        end if;
+    end process runProc;
+
+    count_out <=std_logic_vector(count);
+    max_unsigned<=unsigned(max_count);
+end behave;
+                
+
+
diff --git a/full6seg7.vhd b/full6seg7.vhd
new file mode 100755
index 0000000..0e831a4
--- /dev/null
+++ b/full6seg7.vhd
@@ -0,0 +1,89 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+
+entity full6seg7 is
+port(
+    clk         :in std_logic;
+    areset_l    :in std_logic;
+    value_in    :in std_logic_vector(23 downto 0);
+    dec_value   :in std_logic_vector(5 downto 0) :="000000";
+    hex_out0    :out std_logic_vector(7 downto 0);
+    hex_out1    :out std_logic_vector(7 downto 0);
+    hex_out2    :out std_logic_vector(7 downto 0);
+    hex_out3    :out std_logic_vector(7 downto 0);
+    hex_out4    :out std_logic_vector(7 downto 0);
+    hex_out5    :out std_logic_vector(7 downto 0)
+);
+end full6seg7; 
+
+architecture wrapper of full6seg7 is
+
+    component seg7Driver is
+    port(
+        clk:   in std_logic;
+        rst_l: in std_logic;
+        dec:   in std_logic;
+        cnt:   in std_logic_vector(3 downto 0);   --current count from counter modules
+        seg7: out std_logic_vector(7 downto 0)
+        );
+    end component;
+
+begin
+    seg0 : seg7Driver
+    port map(
+        clk         =>clk,
+        rst_l       =>areset_l,
+        dec         =>dec_value(0),
+        cnt         =>value_in(3 downto 0),
+        seg7        =>hex_out0
+    );
+
+    seg1 : seg7Driver
+    port map(
+        clk         =>clk,
+        rst_l       =>areset_l,
+        dec         =>dec_value(1),
+        cnt         =>value_in(7 downto 4),
+        seg7        =>hex_out1
+    );
+    seg2 : seg7Driver
+    port map(
+        clk         =>clk,
+        rst_l       =>areset_l,
+        dec         =>dec_value(2),
+        cnt         =>value_in(11 downto 8),
+        seg7        =>hex_out2
+    );
+
+    seg3 : seg7Driver
+    port map(
+        clk         =>clk,
+        rst_l       =>areset_l,
+        dec         =>dec_value(3),
+        cnt         =>value_in(15 downto 12),
+        seg7        =>hex_out3
+    );
+
+    seg4 : seg7Driver
+    port map(
+        clk         =>clk,
+        rst_l       =>areset_l,
+        dec         =>dec_value(4),
+        cnt         =>value_in(19 downto 16),
+        seg7        =>hex_out4
+    );
+
+    seg5 : seg7Driver
+    port map(
+        clk         =>clk,
+        rst_l       =>areset_l,
+        dec         =>dec_value(5),
+        cnt         =>value_in(23 downto 20),
+        seg7        =>hex_out5
+    );
+
+
+
+end wrapper;
+
diff --git a/lfsr.vhd b/lfsr.vhd
new file mode 100755
index 0000000..b0d824f
--- /dev/null
+++ b/lfsr.vhd
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lfsr is 
+    port(
+        clk:   in std_logic;
+        rst_l: in std_logic;
+        gen:   in std_logic;
+        num:   out std_logic_vector(7 downto 0)
+        );
+end entity lfsr;
+
+architecture behavioral of lfsr is
+    signal b: std_logic := '0';
+    signal shift: std_logic_vector(15 downto 0):= X"81A5";
+    signal genrising :std_logic;
+    signal r0   :std_logic;
+    signal r1   :std_logic;
+    --stored from left to right, so 16 is located in LSB
+begin
+    num <= shift(3) & shift(10) & shift(11) & shift(4) & shift(14) & shift(1) & shift(9) & shift(6); --picking 8 bits
+    b <= shift(0) xor shift(1) xor shift(3) xor shift(12);
+    process(clk, gen, rst_l)
+    begin
+        if (rst_l = '0') then
+            shift <= X"81A5";
+        elsif(rising_edge(clk)) then 
+            if(genrising='1') then
+                -- x^16 + x^15 + x^13 + x^4
+                shift <= b & shift(15 downto 1);
+            end if;
+        end if;
+    end process;
+
+    genProc : process(clk, rst_l)
+    begin
+        if(rst_l='0')then
+            r0<='0';
+            r1<='0';
+        elsif(rising_edge(clk))then
+            r0<=gen;
+            r1<=r0;
+        end if;
+    end process genProc;
+    genrising<=not r1 and r0;
+end architecture behavioral;
+
+    
diff --git a/seg7Driver.vhd b/seg7Driver.vhd
new file mode 100755
index 0000000..d043ed4
--- /dev/null
+++ b/seg7Driver.vhd
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity seg7Driver is
+    port(
+        clk:   in std_logic;
+        rst_l: in std_logic;
+        dec:   in std_logic;
+        cnt:   in std_logic_vector(3 downto 0);   --current count from counter modules
+        seg7: out std_logic_vector(7 downto 0)
+        );
+end entity seg7Driver;
+
+--six 7-seg displays:
+-- '.' : 0x80
+-- '0' : 0x3f
+-- '1' : 0x06
+-- '2' : 0x5b
+-- '3' : 0x4f
+-- '4' : 0x66
+-- '5' : 0x6d
+-- '6' : 0x7d
+-- '7' : 0x07
+-- '8' : 0x7f
+-- '9' : 0x6f
+
+architecture behavioral of seg7Driver is 
+    type table is array(0 to 15) of std_logic_vector(6 downto 0);
+    constant segLUT: table := (
+				"0111111", --0
+				"0000110", --1
+				"1011011", --2
+				"1001111", --3
+				"1100110", --4
+				"1101101", --5
+				"1111101", --6
+				"0000111", --7
+				"1111111", --8
+				"1101111", --9
+                "1110111", --A
+                "1111100", --b
+                "0111001", --C
+                "1011110", --d
+                "1111001", --E
+                "1110001"); --F
+    signal table_entry: std_logic_vector(6 downto 0);
+begin
+    seg7 <= not (dec & table_entry);
+    process(clk, rst_l)
+    begin
+        if (rst_l = '0') then         --active low reset
+            table_entry <= segLUT(0);
+        elsif (rising_edge(clk)) then
+            table_entry <= segLUT(to_integer(unsigned(cnt)));
+        end if;
+    end process;
+end architecture behavioral;
diff --git a/vga_hrz.vhd b/vga_hrz.vhd
new file mode 100755
index 0000000..5f03ff7
--- /dev/null
+++ b/vga_hrz.vhd
@@ -0,0 +1,87 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity vga_hrz is
+    port(
+        clk     : in std_logic;
+        rst_l   : in std_logic;
+        data_en : out std_logic;
+        sync_en : out std_logic;
+        trigger : out std_logic
+        );
+end entity;
+
+
+architecture behavioral of vga_hrz is
+    type state_type is (FTP, HSYNC, BKP, PIX);
+    signal current_state, next_state : state_type := FTP;
+    signal clk_cnt : integer := 0;
+    signal cnt_rst : std_logic;
+    begin
+    process(rst_l, clk)
+    begin
+        if (rst_l = '0') then
+            current_state <= FTP;
+            clk_cnt <= 0;
+        elsif (rising_edge(clk)) then
+            current_state <= next_state;
+            if (cnt_rst = '1') then --signals state change from other process
+                clk_cnt <= 0;
+            else
+                clk_cnt <= clk_cnt + 1;
+            end if;
+        end if;
+    end process;
+    process(current_state, clk_cnt)
+    begin
+        case current_state is
+            when FTP =>
+                trigger <= '0';
+                data_en <= '0';
+                sync_en <= '1';
+                if (clk_cnt < 15) then  --16 clks
+                    next_state <= FTP;
+                    cnt_rst <= '0';
+                else
+                    next_state <= HSYNC;
+                    cnt_rst <= '1';
+                end if;
+            when HSYNC =>
+                trigger <= '0';
+                data_en <= '0';
+                sync_en <= '0';
+                if (clk_cnt < 95) then  --96 clks
+                    next_state <= HSYNC;
+                    cnt_rst <= '0';
+                else
+                    next_state <= BKP;
+                    cnt_rst <= '1';
+                end if;
+            when BKP =>
+                trigger <= '0';
+                data_en <= '0';
+                sync_en <= '1';
+                if (clk_cnt < 47) then  --48clks
+                    next_state <= BKP;
+                    cnt_rst <= '0';
+                else
+                    next_state <= PIX;
+                    cnt_rst <= '1';
+                end if;
+            when PIX =>
+                data_en <= '1';
+                sync_en <= '1';
+                if (clk_cnt < 639) then --640 pixels
+                    next_state <= PIX;
+                    trigger <= '0';
+                    cnt_rst <= '0';
+                else
+                    next_state <= FTP;
+                    trigger <= '1';
+                    cnt_rst <= '1';
+                end if;
+       end case;
+   end process;
+end architecture behavioral;