50 lines
1.3 KiB
VHDL
Executable File
50 lines
1.3 KiB
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity lfsr is
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port(
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clk: in std_logic;
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rst_l: in std_logic;
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gen: in std_logic;
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num: out std_logic_vector(7 downto 0)
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);
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end entity lfsr;
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architecture behavioral of lfsr is
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signal b: std_logic := '0';
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signal shift: std_logic_vector(15 downto 0):= X"81A5";
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signal genrising :std_logic;
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signal r0 :std_logic;
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signal r1 :std_logic;
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--stored from left to right, so 16 is located in LSB
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begin
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num <= shift(3) & shift(10) & shift(11) & shift(4) & shift(14) & shift(1) & shift(9) & shift(6); --picking 8 bits
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b <= shift(0) xor shift(1) xor shift(3) xor shift(12);
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process(clk, gen, rst_l)
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begin
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if (rst_l = '0') then
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shift <= X"81A5";
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elsif(rising_edge(clk)) then
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if(genrising='1') then
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-- x^16 + x^15 + x^13 + x^4
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shift <= b & shift(15 downto 1);
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end if;
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end if;
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end process;
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genProc : process(clk, rst_l)
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begin
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if(rst_l='0')then
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r0<='0';
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r1<='0';
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elsif(rising_edge(clk))then
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r0<=gen;
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r1<=r0;
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end if;
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end process genProc;
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genrising<=not r1 and r0;
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end architecture behavioral;
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