88 lines
2.5 KiB
VHDL
Executable File
88 lines
2.5 KiB
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vga_hrz is
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port(
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clk : in std_logic;
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rst_l : in std_logic;
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data_en : out std_logic;
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sync_en : out std_logic;
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trigger : out std_logic
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);
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end entity;
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architecture behavioral of vga_hrz is
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type state_type is (FTP, HSYNC, BKP, PIX);
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signal current_state, next_state : state_type := FTP;
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signal clk_cnt : integer := 0;
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signal cnt_rst : std_logic;
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begin
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process(rst_l, clk)
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begin
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if (rst_l = '0') then
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current_state <= FTP;
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clk_cnt <= 0;
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elsif (rising_edge(clk)) then
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current_state <= next_state;
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if (cnt_rst = '1') then --signals state change from other process
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clk_cnt <= 0;
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else
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clk_cnt <= clk_cnt + 1;
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end if;
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end if;
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end process;
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process(current_state, clk_cnt)
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begin
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case current_state is
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when FTP =>
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trigger <= '0';
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data_en <= '0';
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sync_en <= '1';
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if (clk_cnt < 15) then --16 clks
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next_state <= FTP;
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cnt_rst <= '0';
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else
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next_state <= HSYNC;
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cnt_rst <= '1';
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end if;
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when HSYNC =>
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trigger <= '0';
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data_en <= '0';
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sync_en <= '0';
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if (clk_cnt < 95) then --96 clks
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next_state <= HSYNC;
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cnt_rst <= '0';
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else
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next_state <= BKP;
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cnt_rst <= '1';
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end if;
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when BKP =>
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trigger <= '0';
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data_en <= '0';
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sync_en <= '1';
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if (clk_cnt < 47) then --48clks
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next_state <= BKP;
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cnt_rst <= '0';
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else
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next_state <= PIX;
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cnt_rst <= '1';
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end if;
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when PIX =>
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data_en <= '1';
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sync_en <= '1';
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if (clk_cnt < 639) then --640 pixels
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next_state <= PIX;
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trigger <= '0';
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cnt_rst <= '0';
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else
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next_state <= FTP;
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trigger <= '1';
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cnt_rst <= '1';
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end if;
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end case;
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end process;
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end architecture behavioral;
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