61 lines
1.6 KiB
VHDL
Executable File
61 lines
1.6 KiB
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity counter is
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generic (
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size : integer :=4;
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div : integer :=1
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);
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port(
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clk : in std_logic;
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areset_l : in std_logic;
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enable : in std_logic;
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max_count : in std_logic_vector(size-1 downto 0);
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count_out : out std_logic_vector(size-1 downto 0);
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done : out std_logic
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);
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end counter;
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architecture behave of counter is
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signal max_unsigned : unsigned (size-1 downto 0);
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signal count : unsigned (size-1 downto 0);
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begin
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runProc : process(clk, areset_l)
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variable delay : integer :=0;
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begin
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if(areset_l ='0')then
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count <=(others=>'0');
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delay :=0;
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done<='0';
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elsif(rising_edge(clk))then
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if(enable='1')then
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if(delay=(div-1))then
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delay:=0;
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if(count<max_unsigned)then
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count <=count +1;
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done<='0';
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elsif(count>=max_unsigned)then
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count<=(others=>'0');
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done<='1';
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end if;
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else
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delay:= delay+1;
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done<='0';
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end if;
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else
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delay:=delay;
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count<=count;
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done<='0';
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end if;
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end if;
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end process runProc;
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count_out <=std_logic_vector(count);
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max_unsigned<=unsigned(max_count);
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end behave;
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