library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
	generic (
        size : integer :=4;
        div  : integer :=1
    );
    port(
        clk         : in    std_logic;
        areset_l    : in    std_logic;
        enable      : in    std_logic;
        max_count   : in    std_logic_vector(size-1 downto 0);
        count_out   : out   std_logic_vector(size-1 downto 0);
        done        : out   std_logic
    );
end counter;

architecture behave of counter is
    signal max_unsigned : unsigned (size-1 downto 0);
    signal count : unsigned (size-1 downto 0);
    
begin
    runProc : process(clk, areset_l)
        variable delay : integer :=0;
    begin
        if(areset_l ='0')then
            count <=(others=>'0');
            delay :=0;
            done<='0';
        elsif(rising_edge(clk))then
            if(enable='1')then
                if(delay=(div-1))then
                    delay:=0;
                    if(count<max_unsigned)then
                        count <=count +1;
                        done<='0';
                    elsif(count>=max_unsigned)then
                        count<=(others=>'0');
                        done<='1';
                    end if;
                else
                    delay:= delay+1;
                    done<='0';
                end if;
            else
                delay:=delay;
                count<=count;
                done<='0';
            end if;
        end if;
    end process runProc;

    count_out <=std_logic_vector(count);
    max_unsigned<=unsigned(max_count);
end behave;