90 lines
1.9 KiB
VHDL
Executable File
90 lines
1.9 KiB
VHDL
Executable File
Library IEEE;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity VGA_Vert is
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port(
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clk :in std_logic;
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areset_l :in std_logic;
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trig :in std_logic;
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data_en :out std_logic;
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sync_v :out std_logic
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);
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end VGA_Vert;
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architecture behave of VGA_Vert is
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type state is (sync, data);
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signal PS,NS :state;
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signal count :integer;
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begin
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syncProc : process(clk,areset_l)
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begin
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if(areset_l='0')then
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PS<=sync;
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elsif(rising_edge(clk))then
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PS<=NS;
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end if;
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end process syncProc;
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countProc : process(clk,areset_l,trig)
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begin
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if(areset_l='0')then
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count<=0;
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elsif(rising_edge(clk))then
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if(PS=data and NS=sync)then
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count<=0;
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else
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if(trig='1')then
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count<=count+1;
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end if;
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end if;
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end if;
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end process countProc;
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stateProc : process (PS,count)
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begin
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case PS is
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when sync=>
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if(count>=44)then
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NS<=data;
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else
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NS<=sync;
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end if;
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when data=>
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if(count>=524)then
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NS<=sync;
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else
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NS<=data;
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end if;
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end case;
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end process stateProc;
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outputProc : process(PS, count)
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begin
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case PS is
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when sync =>
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data_en<='0';
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if(count>9 and count<12)then
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sync_v<='0';
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else
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sync_v<='1';
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end if;
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when data=>
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data_en<='1';
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sync_v<='1';
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end case;
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end process outputProc;
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end behave;
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