Library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity VGA_Vert is
    port(
        clk         :in std_logic;
        areset_l    :in std_logic;
        trig        :in std_logic;

        data_en     :out std_logic;
        sync_v      :out std_logic
    );
end VGA_Vert;

architecture behave of VGA_Vert is

    type state is (sync, data);
    signal PS,NS        :state;
    signal count        :integer;


begin

    syncProc : process(clk,areset_l)
    begin
        if(areset_l='0')then
            PS<=sync;
        elsif(rising_edge(clk))then
            PS<=NS;
        end if;
    end process syncProc;

    countProc : process(clk,areset_l,trig)
    begin
        if(areset_l='0')then
            count<=0;
        elsif(rising_edge(clk))then
            if(PS=data and NS=sync)then
                count<=0;
            else
                if(trig='1')then
                    count<=count+1;
                end if;
            end if;
        end if;
    end process countProc;

    stateProc : process (PS,count)
    begin
        case PS is
            when sync=>
                if(count>=44)then
                    NS<=data;
                else
                    NS<=sync;
                end if;
            
            when data=>
                if(count>=524)then
                    NS<=sync;
                else
                    NS<=data;
                end if;

        end case;
    end process stateProc;

    outputProc : process(PS, count)
    begin
        case PS is
            when sync =>
                data_en<='0';
                if(count>9 and count<12)then
                    sync_v<='0';
                else
                    sync_v<='1';
                end if;
            
            when data=>
                data_en<='1';
                sync_v<='1';
            
        end case;
    end process outputProc;
                


end behave;