65 lines
1.3 KiB
VHDL
Executable File
65 lines
1.3 KiB
VHDL
Executable File
Library IEEE;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity VGA_Driver is
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port(
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clk :in std_logic;
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areset_l :in std_logic;
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data_en :out std_logic;
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HSYNC :out std_logic;
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VSYNC :out std_logic
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);
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end VGA_Driver;
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architecture wrapper of VGA_Driver is
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component VGA_Vert is
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port(
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clk :in std_logic;
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areset_l :in std_logic;
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trig :in std_logic;
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data_en :out std_logic;
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sync_v :out std_logic
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);
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end component;
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component vga_hrz is
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port(
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clk : in std_logic;
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rst_l : in std_logic;
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data_en : out std_logic;
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sync_en : out std_logic;
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trigger : out std_logic
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);
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end component;
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signal h_done :std_logic;
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signal v_data_en :std_logic;
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signal h_data_en :std_logic;
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begin
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data_en<=v_data_en and h_data_en;
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Vertical : VGA_Vert
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port map(
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clk =>clk,
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areset_l =>areset_l,
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trig =>h_done,
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data_en =>v_data_en,
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sync_v =>VSYNC
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);
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Horizontal : vga_hrz
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port map(
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clk =>clk,
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rst_l =>areset_l,
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data_en =>h_data_en,
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sync_en =>HSYNC,
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trigger =>h_done
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);
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end wrapper; |