Library IEEE;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity VGA_Driver is
    port(
        clk         :in std_logic;
        areset_l    :in std_logic;

        data_en     :out std_logic;
        HSYNC       :out std_logic;
        VSYNC       :out std_logic
    );
end VGA_Driver;

architecture wrapper of VGA_Driver is

    component  VGA_Vert is
    port(
        clk         :in std_logic;
        areset_l    :in std_logic;
        trig        :in std_logic;
        data_en     :out std_logic;
        sync_v      :out std_logic
    );
    end component;

    component  vga_hrz is
    port(
        clk     : in std_logic;
        rst_l   : in std_logic;
        data_en : out std_logic;
        sync_en : out std_logic;
        trigger : out std_logic
        );
    end component;

    signal h_done       :std_logic;
    signal v_data_en    :std_logic;
    signal h_data_en    :std_logic;

begin

    data_en<=v_data_en and h_data_en;

    Vertical : VGA_Vert
    port map(
        clk         =>clk,
        areset_l    =>areset_l,
        trig        =>h_done,
        data_en     =>v_data_en,
        sync_v      =>VSYNC
    );

    Horizontal : vga_hrz
    port map(
        clk         =>clk,
        rst_l       =>areset_l,
        data_en     =>h_data_en,
        sync_en     =>HSYNC,
        trigger     =>h_done
    );


end wrapper;