library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity full6seg7 is
port(
    clk         :in std_logic;
    areset_l    :in std_logic;
    value_in    :in std_logic_vector(23 downto 0);
    dec_value   :in std_logic_vector(5 downto 0) :="000000";
    hex_out0    :out std_logic_vector(7 downto 0);
    hex_out1    :out std_logic_vector(7 downto 0);
    hex_out2    :out std_logic_vector(7 downto 0);
    hex_out3    :out std_logic_vector(7 downto 0);
    hex_out4    :out std_logic_vector(7 downto 0);
    hex_out5    :out std_logic_vector(7 downto 0)
);
end full6seg7; 

architecture wrapper of full6seg7 is

    component seg7Driver is
    port(
        clk:   in std_logic;
        rst_l: in std_logic;
        dec:   in std_logic;
        cnt:   in std_logic_vector(3 downto 0);   --current count from counter modules
        seg7: out std_logic_vector(7 downto 0)
        );
    end component;

begin
    seg0 : seg7Driver
    port map(
        clk         =>clk,
        rst_l       =>areset_l,
        dec         =>dec_value(0),
        cnt         =>value_in(3 downto 0),
        seg7        =>hex_out0
    );

    seg1 : seg7Driver
    port map(
        clk         =>clk,
        rst_l       =>areset_l,
        dec         =>dec_value(1),
        cnt         =>value_in(7 downto 4),
        seg7        =>hex_out1
    );
    seg2 : seg7Driver
    port map(
        clk         =>clk,
        rst_l       =>areset_l,
        dec         =>dec_value(2),
        cnt         =>value_in(11 downto 8),
        seg7        =>hex_out2
    );

    seg3 : seg7Driver
    port map(
        clk         =>clk,
        rst_l       =>areset_l,
        dec         =>dec_value(3),
        cnt         =>value_in(15 downto 12),
        seg7        =>hex_out3
    );

    seg4 : seg7Driver
    port map(
        clk         =>clk,
        rst_l       =>areset_l,
        dec         =>dec_value(4),
        cnt         =>value_in(19 downto 16),
        seg7        =>hex_out4
    );

    seg5 : seg7Driver
    port map(
        clk         =>clk,
        rst_l       =>areset_l,
        dec         =>dec_value(5),
        cnt         =>value_in(23 downto 20),
        seg7        =>hex_out5
    );



end wrapper;