library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity vga_hrz is
    port(
        clk     : in std_logic;
        rst_l   : in std_logic;
        data_en : out std_logic;
        sync_en : out std_logic;
        trigger : out std_logic
        );
end entity;


architecture behavioral of vga_hrz is
    type state_type is (FTP, HSYNC, BKP, PIX);
    signal current_state, next_state : state_type := FTP;
    signal clk_cnt : integer := 0;
    signal cnt_rst : std_logic;
    begin
    process(rst_l, clk)
    begin
        if (rst_l = '0') then
            current_state <= FTP;
            clk_cnt <= 0;
        elsif (rising_edge(clk)) then
            current_state <= next_state;
            if (cnt_rst = '1') then --signals state change from other process
                clk_cnt <= 0;
            else
                clk_cnt <= clk_cnt + 1;
            end if;
        end if;
    end process;
    process(current_state, clk_cnt)
    begin
        case current_state is
            when FTP =>
                trigger <= '0';
                data_en <= '0';
                sync_en <= '1';
                if (clk_cnt < 15) then  --16 clks
                    next_state <= FTP;
                    cnt_rst <= '0';
                else
                    next_state <= HSYNC;
                    cnt_rst <= '1';
                end if;
            when HSYNC =>
                trigger <= '0';
                data_en <= '0';
                sync_en <= '0';
                if (clk_cnt < 95) then  --96 clks
                    next_state <= HSYNC;
                    cnt_rst <= '0';
                else
                    next_state <= BKP;
                    cnt_rst <= '1';
                end if;
            when BKP =>
                trigger <= '0';
                data_en <= '0';
                sync_en <= '1';
                if (clk_cnt < 47) then  --48clks
                    next_state <= BKP;
                    cnt_rst <= '0';
                else
                    next_state <= PIX;
                    cnt_rst <= '1';
                end if;
            when PIX =>
                data_en <= '1';
                sync_en <= '1';
                if (clk_cnt < 639) then --640 pixels
                    next_state <= PIX;
                    trigger <= '0';
                    cnt_rst <= '0';
                else
                    next_state <= FTP;
                    trigger <= '1';
                    cnt_rst <= '1';
                end if;
       end case;
   end process;
end architecture behavioral;