library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seg7Driver is
    port(
        clk:   in std_logic;
        rst_l: in std_logic;
        dec:   in std_logic;
        cnt:   in std_logic_vector(3 downto 0);   --current count from counter modules
        seg7: out std_logic_vector(7 downto 0)
        );
end entity seg7Driver;

--six 7-seg displays:
-- '.' : 0x80
-- '0' : 0x3f
-- '1' : 0x06
-- '2' : 0x5b
-- '3' : 0x4f
-- '4' : 0x66
-- '5' : 0x6d
-- '6' : 0x7d
-- '7' : 0x07
-- '8' : 0x7f
-- '9' : 0x6f

architecture behavioral of seg7Driver is 
    type table is array(0 to 15) of std_logic_vector(6 downto 0);
    constant segLUT: table := (
				"0111111", --0
				"0000110", --1
				"1011011", --2
				"1001111", --3
				"1100110", --4
				"1101101", --5
				"1111101", --6
				"0000111", --7
				"1111111", --8
				"1101111", --9
                "1110111", --A
                "1111100", --b
                "0111001", --C
                "1011110", --d
                "1111001", --E
                "1110001"); --F
    signal table_entry: std_logic_vector(6 downto 0);
begin
    seg7 <= not (dec & table_entry);
    process(clk, rst_l)
    begin
        if (rst_l = '0') then         --active low reset
            table_entry <= segLUT(0);
        elsif (rising_edge(clk)) then
            table_entry <= segLUT(to_integer(unsigned(cnt)));
        end if;
    end process;
end architecture behavioral;