library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lfsr is 
    port(
        clk:   in std_logic;
        rst_l: in std_logic;
        gen:   in std_logic;
        num:   out std_logic_vector(7 downto 0)
        );
end entity lfsr;

architecture behavioral of lfsr is
    signal b: std_logic := '0';
    signal shift: std_logic_vector(15 downto 0):= X"81A5";
    signal genrising :std_logic;
    signal r0   :std_logic;
    signal r1   :std_logic;
    --stored from left to right, so 16 is located in LSB
begin
    num <= shift(3) & shift(10) & shift(11) & shift(4) & shift(14) & shift(1) & shift(9) & shift(6); --picking 8 bits
    b <= shift(0) xor shift(1) xor shift(3) xor shift(12);
    process(clk, gen, rst_l)
    begin
        if (rst_l = '0') then
            shift <= X"81A5";
        elsif(rising_edge(clk)) then 
            if(genrising='1') then
                -- x^16 + x^15 + x^13 + x^4
                shift <= b & shift(15 downto 1);
            end if;
        end if;
    end process;

    genProc : process(clk, rst_l)
    begin
        if(rst_l='0')then
            r0<='0';
            r1<='0';
        elsif(rising_edge(clk))then
            r0<=gen;
            r1<=r0;
        end if;
    end process genProc;
    genrising<=not r1 and r0;
end architecture behavioral;